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MITSUBISHI DIGITAL ASSP MITSUBISHI DIGITAL ASSP
M66256FP M66256FP
5120 x 8-BIT LINE MEMORY (FIFO) 5120 x 8-BIT LINE MEMORY (FIFO)
DESCRIPTION The M66256FP is a high-speed line memory with a FIFO (First In First Out) structure of 5120-word x 8-bit configuration which uses high-performance silicon gate CMOS process technology. It has separate clock, enable and reset signals for write and read, and is most suitable as a buffer memory between devices with different data processing throughput. FEATURES * Memory configuration ........................................................ ............................. 5120 words x 8-bits (dynamic memory) * High-speed cycle ............................................. 25ns (Min.) * High-speed access ......................................... 18ns (Max.) * Output hold ........................................................ 3ns (Min.) * Fully independent, asynchronous write and read operations * Variable length delay bit * Output .................................................................... 3 states APPLICATION Digital photocopiers, high-speed facsimile, laser beam printers.
PIN CONFIGURATION (TOP VIEW)
Q0 1 Q1 2 DATA OUTPUT Q2 3 Q3 4 READ ENABLE INPUT RE 5
24 D0 23 D1 22 D2 21 D3 20 WE WRITE ENABLE INPUT DATA INPUT
M66256FP
READ RESET INPUT RRES 6 GND 7 READ CLOCK INPUT RCK 8 Q4 9 Q5 10 DATA OUTPUT Q6 11 Q7 12
19 WRES WRITE RESET INPUT 18 VCC 17 WCK WRITE CLOCK INPUT 16 D4 15 D5 14 D6 13 D7 DATA INPUT
Outline 24P2U-A
BLOCK DIAGRAM
DATA INPUT D0 ~ D7 13 14 15 16 21 22 23 24
DATA OUTPUT Q0 ~ Q7 1 2 3 4 9 10 11 12
INPUT BUFFER
OUTPUT BUFFER
READ ADDRESS COUNTER
WRITE ADDRESS COUNTER
WRITE CONTROL CIRCUIT
WRITE ENABLE INPUT WE 20 WRITE RESET INPUT WRES 19 WRITE CLOCK INPUT WCK 17
READ CONTROL CIRCUIT
5 RE
READ ENABLE INPUT
MEMORY ARRAY OF 5120-WORD x 8-BIT CONFIGURATION
READ 6 RRES RESET INPUT READ 8 RCK CLOCK INPUT
VCC 18
7 GND
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MITSUBISHI DIGITAL ASSP
M66256FP
5120 x 8-BIT LINE MEMORY (FIFO) FUNCTION When write enable input WE is "L", the contents of data inputs D0 to D7 are written into memory in synchronization with rise edge of write clock input WCK. At this time, the write address counter is also incremented simultaneously. The write function given below are also performed in synchronization with rise edge of WCK. When WE is "H", a write operation to memory is inhibited and the write address counter is stopped. When write reset input WRES is "L", the write address counter is initialized. When read enable input RE is "L", the contents of memory are output to data outputs Q0 to Q7 in synchronization with rise edge of read clock input RCK. At this time, the read address counter is also incremented simultaneously. The read functions given below are also performed in synchronization with rise edge of RCK. When RE is "H", a read operation from memory is inhibited and the read address counter is stopped. The outputs are in the high impedance state. When read reset input RRES is "L", the read address counter is initialized.
ABSOLUTE MAXIMUM RATINGS (Ta = 0 ~ 70C, unless otherwise noted)
Symbol VCC VI VO Pd Tstg Parameter Supply voltage Input voltage Output voltage Maximum power dissipation Storage temperature Conditions A value based on GND pin Ta = 25C Ratings -0.5 ~ +7.0 -0.5 ~ VCC + 0.5 -0.5 ~ VCC + 0.5 440 -65 ~ 150 Unit V V V mW C
RECOMMENDED OPERATING CONDITIONS
Symbol VCC GND Topr Parameter Supply voltage Supply voltage Operating ambient temperature Min. 4.5 0 Limits Typ. 5 0 Max. 5.5 70 Unit V V C
ELECTRICAL CHARACTERISTICS (Ta = 0 ~ 70C, VCC = 5V 10%, GND = 0V)
Symbol VIH VIL VOH VOL IIH Parameter "H" input voltage "L" input voltage "H" output voltage "L" output voltage "H" input current Test conditions Min. 2.0 VCC-0.8 0.55 WE, WRES, WCK, RE, RRES, RCK, D0 ~ D7 WE, WRES, WCK, RE, RRES, RCK, D0 ~ D7 1.0 Limits Typ. Max. 0.8 IOH = -4mA IOL = 4mA VI = VCC Unit V V V V mA
IIL IOZH IOZL ICC CI CO
"L" input current Off state "H" output current Off state "L" output current Operating mean current dissipation Input capacitance Off state output capacitance
VI = GND
-1.0 5.0 -5.0 80 10 15
mA mA mA mA pF pF
VO = VCC VO = GND VI = VCC, GND, Output open tWCK, tRCK = 25ns f = 1MHz f = 1MHz
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MITSUBISHI DIGITAL ASSP
M66256FP
5120 x 8-BIT LINE MEMORY (FIFO) SWITCHING CHARACTERISTICS (Ta = 0 ~ 70C, VCC = 5V 10%, GND = 0V)
Symbol tAC tOH tOEN tODIS Access time Output hold time Output enable time Output disable time Parameter Min. 3 3 3 Limits Typ. Max. 18 18 18 Unit ns ns ns ns
TIMING CONDITIONS (Ta = 0 ~ 70C, VCC = 5V 10%, GND = 0V, unless otherwise noted)
Symbol tWCK tWCKH tWCKL tRCK tRCKH tRCKL tDS tDH tRESS tRESH tNRESS tNRESH tWES tWEH tNWES tNWEH tRES tREH tNRES tNREH tr, tf tH Parameter Write clock (WCK) cycle Write clock (WCK) "H" pulse width Write clock (WCK) "L" pulse width Read clock (RCK) cycle Read clock (RCK) "H" pulse width Read clock (RCK) "L" pulse width Input data setup time to WCK Input data hold time to WCK Reset setup time to WCK or RCK Reset hold time to WCK or RCK Reset nonselect setup time to WCK or RCK Reset nonselect hold time to WCK or RCK WE setup time to WCK WE hold time to WCK WE nonselect setup time to WCK WE nonselect hold time to WCK RE setup time to RCK RE hold time to RCK RE nonselect setup time to RCK RE nonselect hold time to RCK Input pulse rise/fall time Data hold time (Note 1) Min. 25 11 11 25 11 11 7 3 7 3 7 3 7 3 7 3 7 3 7 3 Limits Typ. Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms
20 20
Notes 1: For 1-line access, the following should be satisfied: WE "H" level period 20ms - 5120 tWCK - WRES "L" level period RE "H" level period 20ms - 5120 tRCK - RRES "L" level period 2: Perform reset operation after turning on power supply.
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MITSUBISHI DIGITAL ASSP
M66256FP
5120 x 8-BIT LINE MEMORY (FIFO)
TEST CIRCUIT
VCC
RL=1k
Qn
SW1
CL=30pF : tAC, tOH
Qn SW2 CL=5pF : tOEN, tODIS RL=1k
Input pulse level : Input pulse rise/fall time : Decision voltage input : Decision voltage output :
0 ~ 3V 3ns 1.3V 1.3V (However, tODIS(LZ) is 10% of output amplitude and tODIS(HZ) is 90% of that for decision). The load capacitance CL includes the floating capacitance of connection and the input capacitance of probe.
Parameter tODIS(LZ) tODIS(HZ) tOEN(ZL) tOEN(ZH)
SW1 Closed Open Closed Open
SW2 Open Closed Open Closed
tODIS/tOEN TEST CONDITION
3V RCK 1.3V 1.3V GND
3V RE GND tODIS(HZ) tOEN(ZH) VOH 1.3V
Qn
90%
tODIS(LZ)
tOEN(ZL)
Qn
1.3V 10% VOL
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MITSUBISHI DIGITAL ASSP
M66256FP
5120 x 8-BIT LINE MEMORY (FIFO) OPERATING TIMING * Write cycle
Cycle n
Cycle n+1
Cycle n+2
Disable cycle
Cycle n+3
Cycle n+4
WCK tWCK tWCKH tWCKL tWEH tNWES tNWEH tWES
WE
tDS tDH
tDS tDH
Dn
(n)
( n+1)
(n+2)
(n+3)
(n+4)
WRES = "H"
* Write reset cycle
Cycle n-1
Cycle n
Reset cycle
Cycle 0
Cycle 1
Cycle 2
WCK tWCK tNRESH tRESS tRESH tNRESS
WRES
tDS tDH
tDS tDH
Dn
(n-1)
(n)
(0)
(1)
(2)
WE = "L"
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MITSUBISHI DIGITAL ASSP
M66256FP
5120 x 8-BIT LINE MEMORY (FIFO)
* Matters that needs attention when WCK stops
n cycle
n+1 cycle
n cycle
Disable cycle
WCK tWCK tNWES
WE
tDS tDH
tDS tDH
Dn
(n)
(n)
Period for writing data (n) into memory
Period for writing data (n) into memory
WRES = "H"
Input data of n cycle is read at the rising edge after WCK of n cycle and writing operation starts in the WCK low-level period of n+1 cycle. The writing operation is complete at the falling edge after n+1 cycle. To stop reading write data at n cycle, enter WCK before the rising edge after n+1 cycle. When the cycle next to n cycle is a disable cycle, WCK for a cycle requires to be entered after the disable cycle as well.
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MITSUBISHI DIGITAL ASSP
M66256FP
5120 x 8-BIT LINE MEMORY (FIFO) * Read cycle
Cycle n
Cycle n+1
Cycle n+2
Disable cycle
Cycle n+3
Cycle n+4
RCK tRCK tRCKH tRCKL tREH tNRES tNREH tRES
tAC RE
tODIS
tOEN
HIGH-Z Qn (n) (n+1) (n+2) (n+3) tOH (n+4)
RRES = "H"
* Read reset cycle
Cycle n-1
Cycle n
Reset cycle
Cycle 0
Cycle 1
Cycle 2
RCK tRCK tNRESH tRESS tRESH tNRESS
RRES
tAC
Qn
(n-1)
(n)
(0)
(0)
(0) tOH
(1)
(2)
RE = "L"
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MITSUBISHI DIGITAL ASSP
M66256FP
5120 x 8-BIT LINE MEMORY (FIFO) VARIABLE LENGTH DELAY BITS * 1-line (5120 bits) delay A write input data is written into memory at the second rise edge of WCK in the cycle, and a read output data is output from memory at the first rise edge of RCK in the cycle, so that 1-line delay can be made easily.
Cycle 0 WCK RCK tRESS tRESH
Cycle 1
Cycle 2
Cycle 5118 Cycle 5119
Cycle 5120 Cycle 5121 Cycle 5122 (0') (1') (2')
WRES RRES tDS tDH tDS tDH
Dn
(0)
(1)
(2)
(5117)
(5118)
(5119)
(0')
(1')
(2')
(3')
5120 cycles
tAC
tOH
Qn
(0)
(1)
(2)
(3)
WE, RE = "L"
* N-bit delay bit (Making a reset at a cycle corresponding to delay length)
Cycle 0 WCK RCK tRESS tRESH
Cycle 1
Cycle 2
Cycle n-2
Cycle n-1
Cycle n (0')
Cycle n+1 Cycle n+2 (1') (2')
Cycle n+3 (3')
tRESS tRESH
WRES RRES tDS tDH tDS tDH
Dn
(0)
(1)
(2)
(n-3)
(n-2)
(n-1)
(0')
(1')
(2')
(3')
m cycles
tAC
tOH
Qn
(0)
(1)
(2)
(3)
WE, RE = "L" m3
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MITSUBISHI DIGITAL ASSP
M66256FP
5120 x 8-BIT LINE MEMORY (FIFO) * N-bit delay 2 _____ _____ (Sliding WRES and RRES at a cycle corresponding to delay length)
Cycle 0 WCK RCK tRESS tRESH
Cycle 1
Cycle 2
Cycle n-2
Cycle n-1
Cycle n
Cycle n+1 Cycle n+2
Cycle n+3
WRES tRESS tRESH
RRES
tDS tDH
tDS tDH
Dn
(0)
(1)
(2)
(n-2)
(n-1) tAC
(n) tOH
(n+1)
(n+2)
(n+3)
m cycles
Qn
(0)
(1)
(2)
(3)
WE, RE = "L" m3
* N-bit delay __ 3 (Disabling RE at a cycle corresponding to delay length)
Cycle 0 WCK RCK tRESS tRESH
Cycle 1
Cycle 2
Cycle n-1
Cycle n
Cycle n+1 Cycle n+2
Cycle n+3
WRES RRES tNREH tRES
RE tDS tDH tDS tDH
Dn
(0)
(1)
(2)
(n-2)
(n-1) tAC
(n) tOH
(n+1)
(n+2)
(n+3)
m cycles HIGH-Z Qn
(0)
(1)
(2)
(3)
WE = "L" m3
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MITSUBISHI DIGITAL ASSP
M66256FP
5120 x 8-BIT LINE MEMORY (FIFO) * Shortest read of data "n" written in cycle n Cycle n-1 on read side should be started after end of cycle n+1 on write side When the start of cycle n-1 on read side is earlier than the end of cycle n+1 on write side, output Qn of cycle n becomes invalid. In the figure shown below, the read of cycle n-1 is invalid.
Cycle n WCK
Cycle n+1
Cycle n+2
Cycle n+3
Dn
(n)
(n+1)
(n+2)
(n+3)
Cycle n-2
Cycle n-1
Cycle n
RCK
Qn
invalid
(n)
* Longest read of data "n" written in cycle n: 1-line delay Cycle n <1>* on read side should be started when cycle n <2>* on write is started Output Qn of n cycle <1>* can be read until the start of reading side n cycle <1>* and the start of writing side n cycle <2>* overlap each other.
Cycle n <1>* WCK
Cycle 0 <2>*
Cycle n <2>*
Dn
(n-1)<1>*
(n)<1>*
(00) <2>*
(n-1)<2>*
(n)<2>*
Cycle n <0>* RCK
Cycle 0 <1>*
Cycle n <1>*
Qn
(n-1)<0>*
(n)<0>*
(0)<1>*
(n-1)<1>*
(n)<1>*
<0>*, <1>* and <2>* indicates a line value.
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MITSUBISHI DIGITAL ASSP
M66256FP
5120 x 8-BIT LINE MEMORY (FIFO)
APPLICATION EXAMPLE Laplacian Filter Circuit for Correction of Resolution in the Secondary Scanning Direction.
M66256
N Line n image data
D0
~
Q0
~ Adder N+K {2N-(A+B)}
B Line (n+1) image data
D9
Q9
x2
Corrected image data
1-line delay
Subtractor 2N-(A+B)
xK
M66256 A Line (n-1) image data
D0 D9
~
Q0 Q9
~
1-line delay
Secondary scanning direction
Primary scanning direction
A N B
Line (n-1) Line n Line (n+1) N' = N+K {(N-A)+(N-B)} = N+K {2N-(A+B)} K : Laplacean coefficient
Adder A+B
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